1. Field of the Invention
The invention relates to a digital computer memory and, more specifically, to a random access memory (RAM) that may be reset or flushed in one clock cycle.
2. Art Background
Random access memories (RAM) are common devices used in computers and many other digital systems. Often, it is desirable to reset or flush an entire block of RAM to the same value, either a zero or a one. A computer program may access an area of RAM on the assumption that it contains only zeros while a previous program may have filled the area with various values. Thus, upon program initialization, the memory area must be reset. Other examples also exist where an area of memory must be set to the same value for proper system operation.
Due to the structure of RAM, prior art methods of resetting an area of RAM to one value are time intensive or require an increase in the size of the memory. A RAM is typically in the form of a rectangular array where each memory location comprises a bit which is accessed individually through its row address and column address. A bit in the RAM is accessed during one clock cycle, and, due to power limitations, the bits must be accessed individually. Thus, since each bit must be individually reset and only one bit is accessed per clock cycle, it requires N.times.M clock cycles to reset a memory array with N rows and M columns, or N.times.M bits. Thus, to reset a large memory array requires a large amount of computer time, which slows the operation of the computer system.
Another prior art method resets all of the bits in a RAM in one cycle by adding a large driver transistor to every column in the RAM memory. The prior art techniques that reset all of the bits in a RAM in one cycle require a relatively large amount of power and thus require this additional transistor in every column. The addition of these driver transistors also increases memory size and power consumption.
As will be described, the present invention overcomes the limitations of the prior art by providing a method and apparatus for resetting all of the bits in a RAM memory array to one value during a single clock cycle, without increasing the size of the memory.